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MEMSnet Home: MEMS-Talk: KOH etching large dimension membrane in SOI wafer
KOH etching large dimension membrane in SOI wafer
2004-03-24
Lijun Jiang
KOH etching large dimension membrane in SOI wafer
Lijun Jiang
2004-03-24
Dear all:

I want to make a large and thin membrane of SC-Si by
KOH etching a SOI wafer. The dimension of the membrane
is about 5mmx5mm square. The SOI wafer has 350nm Si
layer + 1um buried oxide. I use 100nm LPCVD SiN as
protective layer on both side. I etched from backside
with square pattern of 5mmx5mm in SiN. I hope that the
1um buried oxide will act as a stop layer. So finally
I will get a membrane with 100nm SiN + 350nm Si + 1um
SiO2, of 5mmx5mm size, supported by bulk SOI
substrate.

Now I have several questions:

1st, is the membrane of such aspect ratio too fragile
that the stress in it will cause it broken? in other
word, is there anybody have made structure like this?

2nd, it seems that the Si at the edge of the square
etched much faster than in the middle, so it reaches
the buried SiO2 earlier. as a result, I got a
structure of a Si pyramid suspended with thin SiO2+Si
membrane, it broken by itself. also the stress at the
edge seems to cause the SiO2 etch very fast. It lost
the function as a stop layer.

Any comment is welcome and appreciated.

Lijun


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