Hi all,
I need some information about vertical etching in 110 silicon wafers. I am
trying to etch  silicon wafers for obtaining vertical walls. My wafers are
4-inch, p-type with a primary flat and a secondary  flat. I have 30 micron x 5
micron rectangular array patterns and each rectangle is separated from its
neighboring rectangle by 5 microns. I was aligning my rectangle sides parallel
to the secondary  flat of the wafer. The masking layer in between the rectangles
(tried oxide and oxinitride masking layers on my wafers) is getting under etched
and after 1 hour etching in KOH or EDP, my masking layer is disappearing and all
the patterns are getting messed up. How should I align my patterns inorder to
get vertical etching atleast 50 microns deep? Any information would be helpful.

Thanks,
Sri




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