> I am process restricted to using a 400 um thick silicon wafer but
> require a thickness of 300 um.  Is there a possibility of using some
> kind of post-processing "grinding" step or something similar to achieve
> this? What would be the practical concerns of performing this if it is
> possible?

Craig,

grinding wafers down after completed process is a standard operation e.g.
for high power MOS devices. There are several vendors for commercial wafer
grinders. Concern is residual stress, which is usually dealt with by
chemically or plasma etching of the last 30um or so, and handling,
as the grinding produces a razor-sharp wafer edge.

You may also consider using substrate carriers to enable your processes to
deal with thinner substrates from the beginning.

regards
klaus
--
Klaus Beschorner
Metron Technology Europe, PVD (Eclipse) Process Manager
Drosselweg 6,71120 Grafenau,Germany. Tel +49-7033-45683