Brent,

    Your best bet is either grayscale litho or RIE-lag based etch processes.
There's lots of literature on grayscale and it works well, but photomask
cost might be rather high and process tuning may take a bit of effort.
RIE-lag based processes exploit the variation of etch rate with mask opening
size and aspect ratio to produce varying etch depths using only a single
masking and etching step. We wrote a paper on one variation of this theme a
while back (Appl Phys Lett, vol 85, #25, 20 Dec 2004, pp. 6281-83). These
kinds of  processes also may take a bit of tuning, especially if you need to
define a highly precise linear slope with mininal surface roughness. You
will also need to consider the effect of the process on other structures
that may be included in the device structure, e.g. most RIE-lag based
processes rely on isotropic etching to clear the superstructure above the
etched floor, thus you need to consider the effects of this isotropic
etching on any other device structures that may be present.

Masa




> Message: 5
> Date: Wed, 19 Apr 2006 21:44:53 -0400
> From: "garber@engr.uconn.edu" 
> Subject: [mems-talk] Silicon Ramp Needed
> To: mems-talk@memsnet.org
> Message-ID: <380-22006442014453567@M2W067.mail2web.com>
> Content-Type: text/plain; charset=iso-8859-1
>
> OK Mems people, work with me. This is a real question.  How can I make a
> silicon ramp 5um tall on one end and 1um on the other, 250um long, 5um
> wide?  I'm starting with a 5um layer of Si on a substrate.  The real
> question is how to etch/make a smooth, ramp, type structure.  I feel a few
> lith steps of 1um 4 times to build "stairs" and then figure a way to
smooth
> the 1um steps.  Anyone????
>
> Brent