A MEMS Clearinghouse® and information portal
for the MEMS and Nanotechnology community
RegisterSign-In
MEMSnet Home About Us What is MEMS? Beginner's Guide Discussion Groups Advertise Here
News
MEMSnet Home: MEMS-Talk: Cu Plating Vias
Cu Plating Vias
2006-06-07
Isibhakhomen Umolu Abhulimen
2006-06-07
Rybnicek, Kimon
Cu Plating Vias
Isibhakhomen Umolu Abhulimen
2006-06-07
Dear All,

I fabricated vias with tapered sidewalls (85- 87 degrees), 20 um in diameter and
a depth of 140 um. I am having problem Cu plating these vias because I have no
conformal Cu seed layer at the bottom and sidewalls of the vias. The Cu seed
layer is deposited using PECVD at a pressure of 5mTorr. Has anyone seen this
problem and how did you solve it?

Thanks for your help.

Isi


reply
Events
Glossary
Materials
Links
MEMS-talk
Terms of Use | Contact Us | Search
MEMS Exchange
MEMS Industry Group
Coventor
Harrick Plasma
Tanner EDA
Addison Engineering
The Branford Group
Process Variations in Microsystems Manufacturing
Tanner EDA by Mentor Graphics