Dear All,

I am working on a device project and have problems with SiO2 window opening.
Baiscally what I'm doing is deposite a layer of 250 nm SiO2 by PECVD on the
fabricated  devices, then open a 10 by 10 micron window by etching SiO2 down
to the gold contacts of each device, and finally connect several devices
together. The problem  I found is that it seems the window can not be etched
very clean, because after I connect them together, there is a huge
resistance related with the connection.

I tried the following recipes:

Method 1: plasma etching.
Plasma thermal ICP 790, RF1=150W, RF2=300W, CF4=20 sccm, P=10 mT. After 3 to
4 mintues etching, SiO2 is completely removed in the window, but I still get
a big resistance.
Question: Does Au react with CF4 and form an insulation layer at the Au
contact top surface? Any method to avoid this?

Methods 2: Wet etching
Surface adhesion promoter AP010 from Silicon Resouces is first spinned on
and bake at 100C for 1 min, then Shipley 1045 photoresist applied. after
photolithography, siloxide etchant (modified BOE) from Transene used for
etching. problem is after 4 mintues etching, the window becomes much bigger
than 10x10 micron, and it also seems have a big resistance.
Questions: (we don't have vapor primer) what's the procedure to inhibit the
SiO2 huge undercut? After etching, do I need to properly clean and how?

I'm eagly waiting for your advise and suggestion. Thanks,

Zhaoyang Fan
Kansas State University