Hi all,

I am testing a capacitive accelerometer. I found the initial capacitance from
chip level testing (~20 pF) was far larger than the one from wafer level testing
(~10 pF). Both the chip level and wafer level testing was done with the same
probe on the same probe station. This phenomenon happened on all chips. Could
anyone tell me why there is so large parasitic capacitance during chip level
testing? Thanks.

Best Regards,

Jin