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MEMSnet Home: MEMS-Talk: why no lift-off for Si processing
why no lift-off for Si processing
2011-02-28
Xiaochen Sun
2011-02-28
Luciani, Vincent
2011-02-28
Andrew Sarangan
2011-03-01
Wilson, Thomas
why no lift-off for Si processing
Wilson, Thomas
2011-03-01
I have an image-reversal bilayer recipe, using LOR10-A and AZ5214E, appropriate
for 1.5 micron thick metal lift-off, but it's not quite finalized. Would you be
able to inform this thread of readers to others? In my case, I don't want to
change photomasks, so I much prefer AZ5214E on the top layer in an image-
reversal mode.



-----Original Message-----
From: [email protected] [mailto:mems-talk-
[email protected]] On Behalf Of Andrew Sarangan
Sent: Monday, February 28, 2011 3:02 PM
To: General MEMS discussion
Subject: Re: [mems-talk] why no lift-off for Si processing

To add what has been said already, many etchants are developed with
silicon in mind. Some may attack III-V semiconductors, or react to
produce undesirable byproducts on the surface (I've had the misfortune
of losing an InSb wafer due to a Cr etchant). If you can blanket coat
and then pattern down, adhesion, step coverage and substrate
cleanliness will be better. You can also heat the substrate, which you
can't if you have resist on it. If chemical selectivity does not allow
for an etch process, then lift-off is the only option. However,
lift-off is not all bad either. It can work very well, even with
sputter deposition, by using a bilayer resist process.

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