Hello everybody,
        I am interested in using XeF2 to etch silicon on a CMOS chip, and
would like to know which MOSIS processes support an open layer of exposed
Si substrate for this etching.  More generally, I'd really like to get
detailed cross-sections and layer thicknesses for CMOS processes available
through MOSIS. Does anyone know where this information might be available?
        Thanks!

        Patrick Bedell
        jpb@mrsc.ucsf.edu
        (415) 476 1910