Thank you for your input Neal, Kirt and Bob.

Just to clarify a bit:
The requirement of low temperature is set by the Parylene C insulation material,
which is able to withstand around 300 degrees centigrade. The reason I can't use
thermal oxide or similar processes for the insulation of the wafer through-holes
is that the wafer through-holes have to be fabricated as a post process on CMOS
wafers (I have considered PECVD TEOS oxide as well, but I'm not sure if the
quality of this material is sufficient).

The wafer through-holes are almost vertical and therefore difficult to coat
using PVD. Though, it might be worth considering a modification of the ICP etch
process in order to provide a tapered profile.

Thanks again,
Frank
------------------------
Frank Engel Rasmussen
Industrial Ph.D. student, MEMS research group
Mikroelektronik Centret
Oersteds Plads
Building 345 (east), DTU
DK-2800 Kgs. Lyngby
Denmark



        -----Oprindelig meddelelse-----
        Fra: Neal Ricks [mailto:[email protected]]
        Sendt: to 15-08-2002 19:37
        Til: [email protected]
        Cc:
        Emne: Re: [mems-talk] CVD deposition of metal needed !



        Hello Frank,
        Is the reason for specifying CVD that through-hole profile very
vertical, causing step coverage difficulties, in addition to the temperature
constraints upon the insulator?
        If the holes are tapered, you may be interested in metallizing using a
PVD technique (Al or Cu only).  The substrate temperature should stay low enough
not to degrade the Paralene, provided the required thickness is not too great.
I believe I have evaporated more than a micron of Aluminum while temperature
tape placed upon the back of a 0.5mm thick wafer indicated that it did not
exceed 70C.
        I would be happy to provide this service if you think PVD will work.
        regards,
        Neal Ricks
        Haleos, Inc.  540.552.4610x3875

         Frank Rasmussen wrote:Dear colleagues,

        I am searching for a facility (foundry, university lab, etc.) capable of
depositing metals by means of chemical vapor deposition (CVD). A metal like Al,
Cu or W is preferred.

        If the given process is a LPCVD, PECVD or any other kind of CVD process
is not important. However, the process temperature is important. The maximum
allowable process temperature is 300 degrees centigrade (572 degrees
Fahrenheit), but a temperature below 300 degrees centrigrade is preferred.

        My application is metallization of wafer through-holes, which are
insulated by Parylene C.

        Any input is greatly appreciated.

        Thanks,
        Frank

        ------------------------
        Frank Engel Rasmussen
        Industrial Ph.D. student, MEMS research group
        Mikroelektronik Centret
        Oersteds Plads
        Building 345 (east), DTU
        DK-2800 Kgs. Lyngby
        Denmark
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