> -----Original Message-----
> From: Blunier, Stefan [mailto:stefan.blunier@imes.mavt.ethz.ch]
> Sent: Thursday, January 16, 2003 1:14 PM
> To: mems-talk@memsnet.org
> Subject: [mems-talk] Underetch of SOI
>
> I'm working on SOI wafers developing free hanging structures. During
> underetch with HF (48%) I noticed that the etch velocity of the two
> Si-SiO2 interfaces is different. SiO2 thickness is 3 microns...
> The etch velocity at the interface SiO2-device layer is
> faster than the etch velocity at the interface SupportSi-SiO2.

> Does anybody know this problem

We've had a similar problem with commercial SOI wafers: we had wafers with a 2um
buried oxide layer, and we also saw a fast etch at the device layer/oxide
interface. In another batch of wafers with 1um oxide layer, it was the handle
layer/oxide interface that etched faster. The problem was biggest for the 2um
layer, and there even seemed to be some wafer-to-wafer variation.

> and how to avoid it?

We suspect that it partly is a matter of interface quality, but we haven't done
any further investigations. We also believe that the problem is less severe the
thinner oxide layer you have.


Best regards,

Søren

____________________________
Søren Jensen
Ph.D. Student, MEMS Activity
Mikroelektronik Centret (MIC)
Technical University of Denmark, bldg. 345ø
DK-2800 Kgs. Lyngby
Denmark

www.mic.dtu.dk/research/mems