Hi,

I did something like that before. Parylene will not be attacked by the
KOH but the parylene/silicon interface will be. From what I oberved,
Parylene/SiO2 interface was fine, so what you can do is have a silicon
dioxide "ring" underneath the parylene on the edge of the frontside. If
you are etching through the whole thickness and don't have oxide on the
frontside, the KOH will start to attack the interface (really fast,
about 1mm in 10 minutes). What you can do it stop the KOH etching before
the silicon (say when there's 10 microns left) is competely gone and
finish the etching with gas-phase of plasma etching.

Matthieu

Gang Li wrote:

>Dear all,
>
>Can parylene be used to protect frontside of the wafers when
>you carry on etching trough the wafers from the backside?
>Any information will be appreciated greatly.
>
>Regards,
>
>Li Gang
>
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